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A 12.77-MHz on-chip relaxation oscillator with digital compensation for loop delay variation., , , and . A-SSCC, page 1-4. IEEE, (2015)A novel FPGA implementation of mirror-paradigm RS-based QC-LDPC decoder for NVM channels., , and . ISPACS, page 760-765. IEEE, (2012)A Dual-Feedforward Carrier-Modulated Second-Order Class-D Amplifier With Improved THD., , , and . IEEE Trans. on Circuits and Systems, 59-II (1): 35-39 (2012)A passively compensated capacitive sensor readout with biased varactor temperature compensation and temperature coherent quantization., , , , , and . ISCAS, page 1-4. IEEE, (2017)Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing., , , , and . IEEE Trans. VLSI Syst., 18 (8): 1225-1229 (2010)A 457 nW Near-Threshold Cognitive Multi-Functional ECG Processor for Long-Term Cardiac Monitoring., , , , , , , , , and . J. Solid-State Circuits, 49 (11): 2422-2434 (2014)A 5-Gb/s Automatic Gain Control Amplifier With Temperature Compensation., , , , , and . J. Solid-State Circuits, 47 (6): 1323-1333 (2012)Optimization of codes for the joint Viterbi detector decoder (JVDD)., , and . ICNC, page 1-5. IEEE Computer Society, (2016)A 34-FPS 698-GOP/s/W Binarized Deep Neural Network-Based Natural Scene Text Interpretation Accelerator for Mobile Edge Computing., , , , , , , and . IEEE Trans. Industrial Electronics, 66 (9): 7407-7416 (2019)Asymmetrical Dead-Time Control Driver for Buck Regulator., , , , , , and . IEEE Trans. VLSI Syst., 24 (12): 3543-3547 (2016)