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Disambiguation of "Craninckx, Jan"

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A Fully Reconfigurable Software-Defined Radio Transceiver in 0.13μm CMOS.

, , , , , , , , , , , , and . ISSCC, page 346-607. IEEE, (2007)

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Tim Janz University of Stuttgart

PD Dr. phil. Frank Janle University of Stuttgart

Benedikt Janny

Isabel Janowsky University of Stuttgart

Hon. -Prof. Dr. Martin Jansen University of Stuttgart

 

Other publications of authors with the same name

A design methodology for fully reconfigurable Delta-Sigma data converters., , and . DATE, page 1379-1384. IEEE, (2009)Calibration of Direct-Conversion Transceivers., , , and . J. Sel. Topics Signal Processing, 3 (3): 488-498 (2009)A 2-mm2 0.1-5 GHz Software-Defined Radio Receiver in 45-nm Digital CMOS., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 44 (12): 3486-3498 (2009)Flexible Baseband Analog Circuits for Software-Defined Radio Front-Ends., , , and . J. Solid-State Circuits, 42 (7): 1501-1512 (2007)An Incremental-Charge-Based Digital Transmitter With Built-in Filtering., , , and . J. Solid-State Circuits, 50 (12): 3065-3076 (2015)A 2.4 GHz Low-Power Sixth-Order RF Bandpass ΔΣ Converter in CMOS., , , , , , and . J. Solid-State Circuits, 44 (11): 2873-2880 (2009)New Associate Editors.. J. Solid-State Circuits, 54 (6): 1515-1516 (2019)A 150 kHz-80 MHz BW Discrete-Time Analog Baseband for Software-Defined-Radio Receivers using a 5th-Order IIR LPF, Active FIR and a 10 bit 300 MS/s ADC in 28 nm CMOS., , , , and . J. Solid-State Circuits, 51 (7): 1593-1606 (2016)A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS., , , , and . J. Solid-State Circuits, 45 (10): 2080-2090 (2010)A 86 MHz-12 GHz Digital-Intensive PLL for Software-Defined Radios, Using a 6 fJ/Step TDC in 40 nm Digital CMOS., , , , , and . J. Solid-State Circuits, 45 (10): 2116-2129 (2010)