PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Rossi, Davide"

Author of the publication

copydeleteadd this publication to your clipboard
BioWolf: A Sub-10-mW 8-Channel Advanced Brain-Computer Interface Platform With a Nine-Core Processor and BLE Connectivity.

, , , , , and . IEEE Trans. Biomed. Circuits and Systems, 13 (5): 893-906 (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Edoardo Rossi University of Stuttgart

Davide Padeletti University of Stuttgart

PD Dr. rer. nat. Davide Cesare Veniani University of Stuttgart

 

Other publications of authors with the same name

An Executable Language/Enactment Engine Approach for Designing and Architecting Process-Aware Web Applications., and . IJEBR, 5 (3): 1-13 (2009)A heterogeneous digital signal processor implementation for dynamically reconfigurable computing., , , , and . CICC, page 641-644. IEEE, (2009)Controlled placement of standard cell memory arrays for high density and low power in 28nm FD-SOI., , , , and . ASP-DAC, page 81-86. IEEE, (2015)High performance AXI-4.0 based interconnect for extensible smart memory cubes., , , and . DATE, page 1317-1322. ACM, (2015)A Multi-Agent Process Centered Environment Integrated with the WWW., , and . WETICE, page 113-120. IEEE Computer Society, (1997)Promoting Best Practice Sharing within Organizations., and . WEBIST, page 375-380. SciTePress, (2013)PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision., , , , and . Signal Processing Systems, 84 (3): 339-354 (2016)Supporting authors in documenting and sharing operative knowledge., and . Online Information Review, 42 (4): 451-467 (2018)Power mitigation of a heterogeneous multicore architecture on FPGA/ASIC by DFS/DVFS techniques., , and . Microprocessors and Microsystems - Embedded Hardware Design, (2018)A sub-mW IoT-endnode for always-on visual monitoring and smart triggering., , , and . CoRR, (2017)