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The Impulse Memory Controller., , , , , , , and . IEEE Trans. Computers, 50 (11): 1117-1132 (2001)A Phase-Adaptive Approach to Increasing Cache Performance., , and . PACT, page 432. IEEE Computer Society, (2007)METRIC: Memory tracing via dynamic binary rewriting to identify cache inefficiencies., , , , , and . ACM Trans. Program. Lang. Syst., 29 (2): 12 (2007)Memory Wall., and . Encyclopedia of Parallel Computing, Springer, (2011)An LTE Uplink Receiver PHY benchmark and subframe-based power management., , , , and . ISPASS, page 25-34. IEEE Computer Society, (2012)Caches as Filters: A New Approach to Cache Analysis., , and . MASCOTS, page 2-12. IEEE Computer Society, (1998)Profiling I/O Interrupts in Modern Architectures., , and . MASCOTS, page 115-123. IEEE Computer Society, (2000)Guest Editor's Introduction.. International Journal of Parallel Programming, 35 (3): 179-180 (2007)A Cost Model For Integrated Restructuring Optimizations., , , and . J. Instruction-Level Parallelism, (2003)Improving data access efficiency by using a tagless access buffer (TAB)., , , , , , and . CGO, page 28:1-28:11. IEEE Computer Society, (2013)