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Using a Distributed Rectangle Bin-Packing Approach for Core-based SoC Test Scheduling with Power Constraints.

Y. Xia, M. Chrzanowska-Jeske, B. Wang, and M. Jeske. ICCAD, page 100-106. IEEE Computer Society / ACM, (2003)

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Substrate noise modeling in early floorplanning of MS-SOCs.G. Blakiewicz, M. Jeske, M. Chrzanowska-Jeske, and J. Zhang. ASP-DAC, page 819-823. ACM Press, (2005)Using a Distributed Rectangle Bin-Packing Approach for Core-based SoC Test Scheduling with Power Constraints.Y. Xia, M. Chrzanowska-Jeske, B. Wang, and M. Jeske. ICCAD, page 100-106. IEEE Computer Society / ACM, (2003)Integrated floorplanning with buffer/channel insertion for bus-based designs.F. Rafiq, M. Chrzanowska-Jeske, H. Yang, M. Jeske, and N. Sherwani. IEEE Trans. on CAD of Integrated Circuits and Systems, 22 (6): 730-741 (2003)Substrate noise optimization in early floorplanning for mixed signal SOCs.G. Blakiewicz, M. Jeske, and M. Chrzanowska-Jeske. SoCC, page 301-304. IEEE, (2004)Substrate noise-aware floorplanning for mixed-signal SOCs.M. Jeske, G. Blakiewicz, M. Chrzanowska-Jeske, and B. Wang. ISCAS (2), page 445-448. IEEE, (2004)

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Using a Distributed Rectangle Bin-Packing Approach for Core-based SoC Test Scheduling with Power Constraints.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Using a Distributed Rectangle Bin-Packing Approach for Core-based SoC Test Scheduling with Power Constraints.

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Using a Distributed Rectangle Bin-Packing Approach for Core-based SoC Test Scheduling with Power Constraints.