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An Interactive Verification Tool for Synchronous/Reactive Systems.

, and . MBMV, page 267-277. Institut für Angewandte Mikroelektronik und Datentechnik, Fakultät für Informatik und Elektrotechnik, Universität Rostock, (2013)

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Formale Verifikation eingebetteter Systeme., , , , and . it+ti - Informationstechnik und Technische Informatik, 41 (2): 12-16 (1999)Towards the standardization of plug-and-play devices for model-based designs of embedded systems., and . SIES, page 189-192. IEEE, (2016)Embedding Imperative Synchronous Languages in Interactive Theorem Provers.. ACSD, page 143-. IEEE Computer Society, (2001)Integrating UML Composite Structures and fUML., , and . SOFSEM, volume 8327 of Lecture Notes in Computer Science, page 269-280. Springer, (2014)From LTL to Symbolically Represented Deterministic Automata., and . VMCAI, volume 4905 of Lecture Notes in Computer Science, page 279-293. Springer, (2008)Out-of-Order Execution of Buffered Function Units in Exposed Data Path Architectures., , and . IPDPS Workshops, page 229-234. IEEE Computer Society, (2017)Efficient Handling of Arrays in Dataflow Process Networks., , and . HPCC-ICESS, page 1395-1402. IEEE Computer Society, (2012)Performing causality analysis by bounded model checking., and . ACSD, page 78-87. IEEE, (2008)Desynchronizing Synchronous Programs by Modes., , and . ACSD, page 32-41. IEEE Computer Society, (2009)Round Trip to Asynchrony and Synchrony., and . MBMV, page 239-248. OFFIS-Institut für Informatik, (2011)