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Hardware-software Scalable Architectures for Gaussian Elimination over GF(2) and Higher Galois Fields.

P. Saxena, V. Kumar, D. Singh, H. Narayanan, and S. Patkar. PECCS, page 195-201. SciTePress, (2013)

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B. Schlecht

Manish Kumar University of Stuttgart

Shreya Kumar University of Stuttgart

Tarun Kumar Mitruka Vinod Kumar Mitruka University of Stuttgart

Max B. Schäfer

Other publications of authors with the same name

Hardware-software Scalable Architectures for Gaussian Elimination over GF(2) and Higher Galois Fields.P. Saxena, V. Kumar, D. Singh, H. Narayanan, and S. Patkar. PECCS, page 195-201. SciTePress, (2013)Storage-allocation to sequential structures in High-Level Synthesis-assisted prototyping.V. Kumar, S. Maity, and S. Patkar. ICCD, page 464-469. IEEE Computer Society, (2014)Framework for Application Mapping over Packet-Switched Network of FPGAs: Case Studies.V. Kumar, P. Engineer, M. Datar, Y. Turakhia, S. Agarwal, S. Diwale, and S. Patkar. CoRR, (2015)Parallel two step random walk algorithm to analyze VLSI power grid networks.S. Dash, V. Bangera, V. Kumar, G. Trivedi, and S. Patkar. VDAT, page 1-2. IEEE, (2015)FPGA Based High Performance Double-Precision Matrix Multiplication.V. Kumar, S. Joshi, S. Patkar, and H. Narayanan. International Journal of Parallel Programming, 38 (3-4): 322-338 (2010)Relaxation Based Circuit Simulation Acceleration over CPU-FPGA.V. Kumar, K. Dhiman, M. Datar, A. Pacharne, H. Narayanan, and S. Patkar. VLSI Design, page 409-414. IEEE Computer Society, (2016)Lightweight Forth Programmable NoCs.V. Kumar, D. Shah, M. Datar, and S. Patkar. VLSI Design, page 368-373. IEEE Computer Society, (2018)FPGA-based implementation of M4RM for matrix multiplication over GF(2).V. Kumar, V. Kumar, and S. Patkar. VDAT, page 1-2. IEEE, (2014)FPGA Based High Performance Double-Precision Matrix Multiplication.V. Kumar, S. Joshi, S. Patkar, and H. Narayanan. VLSI Design, page 341-346. IEEE Computer Society, (2009)Projective Geometry and precedence constraint based application mapping on multicore network-on-chip systems.J. Porwal, S. Diwale, V. Kumar, and S. Patkar. VLSI-DAT, page 1-4. IEEE, (2014)

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Disambiguation of "Kumar, Vinay B. Y."

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Hardware-software Scalable Architectures for Gaussian Elimination over GF(2) and Higher Galois Fields.

Please choose a person to relate this publication to

B. Schlecht

Manish Kumar University of Stuttgart

Shreya Kumar University of Stuttgart

Tarun Kumar Mitruka Vinod Kumar Mitruka University of Stuttgart

Max B. Schäfer

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Kumar, Vinay B. Y."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Hardware-software Scalable Architectures for Gaussian Elimination over GF(2) and Higher Galois Fields.

Please choose a person to relate this publication to

B. Schlecht

Manish Kumar University of Stuttgart

Shreya Kumar University of Stuttgart

Tarun Kumar Mitruka Vinod Kumar Mitruka University of Stuttgart

Max B. Schäfer

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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Hardware-software Scalable Architectures for Gaussian Elimination over GF(2) and Higher Galois Fields.