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Circuit CAD Tools as a Security Threat., , and . HOST, page 65-66. IEEE Computer Society, (2008)Functional Design Errors in Digital Circuits - Diagnosis, Correction and Repair, , and . Lecture Notes in Electrical Engineering Springer, (2009)Design, Analysis and Test of Logic Circuits Under Uncertainty, , and . Lecture Notes in Electrical Engineering Springer, (2013)Quantum Circuit Simulation., , and . Springer, (2009)Partitioning-Based Methods., and . Handbook of Algorithms for Physical Design Automation, Auerbach Publications, (2008)On-Chip Test Generation Using Linear Subspaces., , and . European Test Symposium, page 111-116. IEEE Computer Society, (2006)Post-placement rewiring and rebuffering by exhaustive search for functional symmetries., , and . ICCAD, page 56-63. IEEE Computer Society, (2005)Generalized Boolean symmetries through nested partition refinement., , and . ICCAD, page 763-770. IEEE, (2013)Automatic error diagnosis and correction for RTL designs., , , and . HLDVT, page 65-72. IEEE Computer Society, (2007)Improved a priori interconnect predictions and technology extrapolation in the GTX system., , , , , , , and . IEEE Trans. VLSI Syst., 11 (1): 3-14 (2003)