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Resolving the memory bottleneck for single supply near-threshold computing., , , , , and . DATE, page 1-6. European Design and Automation Association, (2014)Sub-threshold custom standard cell library validation., , , and . ISQED, page 257-262. IEEE, (2014)Synthesizable Memory Arrays Based on Logic Gates for Subthreshold Operation in IoT., , , and . IEEE Trans. on Circuits and Systems, 66-I (3): 941-954 (2019)A parametrizable low-power high-throughput turbo-decoder., , and . ICASSP (5), page 25-28. IEEE, (2005)A framework for analyzing the propagation of hardware-induced errors in non-recursive LTI blocks with finite wordlength effects., , and . PATMOS, page 147-154. IEEE, (2016)Physical modeling of bitcell stability in subthreshold SRAMs for leakage-area optimization under PVT variations., , and . ICCAD, page 38. ACM, (2018)PHIDIAS: ultra-low-power holistic design for smart bio-signals computing platforms., , , , , , , , , and 2 other author(s). Conf. Computing Frontiers, page 309-314. ACM, (2016)Reliable and energy-efficient 1MHz 0.4V dynamically reconfigurable SoC for ExG applications in 40nm LP CMOS., , , , , , , , , and 2 other author(s). ISSCC, page 430-431. IEEE, (2013)Variability aware cell library optimization for reliable sub-threshold operation., and . ESSCIRC, page 42-45. IEEE, (2012)On the use of analytical techniques for reliability analysis in presence of hardware-induced errors., , and . INDIN, page 1416-1423. IEEE, (2015)