Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Reconfigurable Circuits Using Magnetic Tunneling Junction Memories.

V. Silva, J. Fernandes, and H. Neto. DoCEIS, volume 314 of IFIP Advances in Information and Communication Technology, page 549-558. Springer, (2010)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

C. Traut

C. Honold

Dr. Torbjörn Cunis University of Stuttgart

Vanessa Costalonga Martins University of Stuttgart

April M. Cooper

Other publications of authors with the same name

Sliding block Viterbi decoders in FPGA.M. Véstias, H. Neto, and H. Sarmento. FPL, page 595-598. IEEE, (2012)Enhancing stochastic computations via process variation.R. Duarte, M. Véstias, and H. Neto. FPL, page 1-7. IEEE, (2015)Macro-Based Hardware Compilation of Java(tm) Bytecodes into a Dynamic Reconfigurable Computing System.J. Cardoso, and H. Neto. FCCM, page 2-11. IEEE Computer Society, (1999)XtokaxtikoX: A stochastic computing-based autonomous cyber-physical system.R. Duarte, H. Neto, and M. Véstias. ICRC, page 1-7. IEEE Computer Society, (2016)Sorting Units for FPGA-Based Embedded Systems.R. Marcelino, H. Neto, and J. Cardoso. DIPES, volume 271 of IFIP, page 11-22. Springer, (2008)Decimal addition on FPGA based on a mixed BCD/excess-6 representation.H. Neto, and M. Véstias. Microprocessors and Microsystems - Embedded Hardware Design, (2017)An Efficient and Scalable Architecture for Neural Networks with Backpropagation Learning.P. Domingos, F. Silva, and H. Neto. FPL, page 89-94. IEEE, (2005)On Reconfigurable Architectures for Efficient Matrix Inversion.G. de Matos, and H. Neto. FPL, page 1-6. IEEE, (2006)Bitwise Encoding of Finite State Machines.J. Monteiro, J. Kukula, S. Devadas, and H. Neto. VLSI Design, page 379-382. IEEE Computer Society, (1994)System-Level Co-Synthesis of Dataflow Dominated Applications on Reconfigurable Hardware/Software Architectures.M. Véstias, and H. Neto. IEEE International Workshop on Rapid System Prototyping, page 130-137. IEEE Computer Society, (2002)