PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Jacome, Margarida F."

Author of the publication

copydeleteadd this publication to your clipboard
A Case Study of a System Level Approach to Exploration of Queuing Management Schemes for Input Queue Packet Switches.

, , and . PDP, page 401-408. IEEE Computer Society, (2003)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

F. Dörr

F. Laufer

F. Rusitschka

F. Perni

F. D{\"o}rr

 

Other publications of authors with the same name

Algorithm and architecture-level design space exploration using hierarchical data flows., and . ASAP, page 272-282. IEEE Computer Society, (1997)Self-Imposed Temporal Redundancy: An Efficient Technique to Enhance the Reliability of Pipelined Functional Units., , and . SBAC-PAD, page 45-53. IEEE Computer Society, (2007)Special issue on power-aware embedded computing., and . ACM Trans. Embedded Comput. Syst., 2 (3): 251-254 (2003)Exploring Performance Tradeoffs for Clustered VLIW ASIPs., , and . ICCAD, page 504-510. IEEE Computer Society, (2000)Compiler-Directed ILP Extraction for Clustered VLIW/EPIC Machines., and . Embedded Software for SoC, Kluwer / Springer, (2003)RS-FDRA: a register sensitive software pipelining algorithm for embedded VLIW processors., and . CODES, page 67-72. ACM, (2001)Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures., , and . HiPEAC, volume 5409 of Lecture Notes in Computer Science, page 324-338. Springer, (2009)Defect tolerant probabilistic design paradigm for nanotechnologies., , , and . DAC, page 596-601. ACM, (2004)Embedded Architect: A Tool for Early Performance Evaluation of Embedded Software., and . ICSE, page 824-825. IEEE Computer Society, (2003)NREC: Risk Assessment and Planning of Complex Designs., and . IEEE Design & Test of Computers, 14 (1): 42-49 (1997)