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s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET.

P. Upadhyaya, C. Poon, S. Lim, J. Cho, A. Roldan, W. Zhang, J. Namkoong, T. Pham, B. Xu, W. Lin, H. Zhang, N. Narang, K. Tan, G. Zhang, Y. Frans, and K. Chang. J. Solid-State Circuits, 54 (1): 18-28 (2019)

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Devanshi Upadhyaya University of Stuttgart

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A new gain controllable on-chip active balun for 5 GHz direct conversion receiver.M. Rajashekharaiah, P. Upadhyaya, D. Heo, and Y. Chen. ISCAS (5), page 5115-5118. IEEE, (2005)A 0.5-16.3 Gbps Multi-Standard Serial Transceiver With 219 mW/Channel in 16-nm FinFET.M. Erett, J. Hudner, D. Carey, R. Casey, K. Geary, K. Hearne, P. Neto, T. Mallard, V. Sooden, M. Smyth and 7 other author(s). J. Solid-State Circuits, 52 (7): 1783-1797 (2017)Design of high-speed wireline transceivers for backplane communications in 28nm CMOS.J. Savoj, K. Hsieh, P. Upadhyaya, F. An, J. Im, X. Jiang, J. Kamali, K. Lai, Z. Wu, E. Alon and 1 other author(s). CICC, page 1-4. IEEE, (2012)Wideband flexible-reach techniques for a 0.5-16.3Gb/s fully-adaptive transceiver in 20nm CMOS.J. Savoj, H. Aslanzadeh, D. Carey, M. Erett, W. Fang, Y. Frans, K. Hsieh, J. Im, A. Jose, D. Turker and 3 other author(s). CICC, page 1-4. IEEE, (2014)A 0.5-16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS.Y. Frans, D. Carey, M. Erett, H. Aslanzadeh, W. Fang, D. Turker, A. Jose, A. Bekele, J. Im, P. Upadhyaya and 4 other author(s). J. Solid-State Circuits, 50 (8): 1932-1944 (2015)A 7-to-18.3GHz compact transformer based VCO in 16nm FinFET.M. Raj, P. Upadhyaya, Y. Frans, and K. Chang. VLSI Circuits, page 1-2. IEEE, (2016)A 40-to-64 Gb/s NRZ Transmitter With Supply-Regulated Front-End in 16 nm FinFET.Y. Frans, S. McLeod, H. Hedayati, M. Elzeftawi, J. Namkoong, W. Lin, J. Im, P. Upadhyaya, and K. Chang. J. Solid-State Circuits, 51 (12): 3167-3177 (2016)A 56Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16nm FinFET.Y. Frans, M. Elzeftawi, H. Hedayati, J. Im, V. Kireev, T. Pham, J. Shin, P. Upadhyaya, L. Zhou, S. Asuncion and 4 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)A 5.3GHz low-phase-noise LC VCO with harmonic filtering resistor.L. Wang, P. Upadhyaya, P. Sun, Y. Zhang, D. Heo, Y. Chen, and D. Jeong. ISCAS, IEEE, (2006)A 0.5-28GB/S Wireline Tranceiver with 15-Tap DFE and Fast-Locking Digital CDR in 7NM FinFET.J. Im, S. Chen, D. Freitas, A. Chou, L. Zhou, I. Zhuang, T. Cronin, D. Mahashin, W. Lin, K. Chan and 7 other author(s). VLSI Circuits, page 145-146. IEEE, (2018)

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A Fully Adaptive 19-58-Gb/s PAM-4 and 9.5-29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET.

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Devanshi Upadhyaya University of Stuttgart

Other publications of authors with the same name

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PUMA

Disambiguation of "Upadhyaya, Parag"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Fully Adaptive 19-58-Gb/s PAM-4 and 9.5-29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET.

Please choose a person to relate this publication to

Devanshi Upadhyaya University of Stuttgart

Other publications of authors with the same name

Disambiguation

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community post
history of this post
URL
DOI
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APA
Chicago
DIN 1505
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A Fully Adaptive 19-58-Gb/s PAM-4 and 9.5-29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET.