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Disambiguation of "Garcia-Gervacio, Jose Luis"

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A design methodology for logic paths tolerant to local intra-die variations.

, , and . ISCAS, page 596-599. IEEE, (2008)

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Prof. Jose Luis Moro University of Stuttgart

Jithin Jose University of Stuttgart

Basil Jose University of Stuttgart

Luis Orozco University of Stuttgart

Luis Mandl University of Stuttgart

 

Other publications of authors with the same name

SCADA system design: A proposal for optimizing a production line., , and . CONIELECOMP, page 192-197. IEEE, (2016)Possibilities of defect-size magnification for testing resistive-opens in nanometer technologies., , and . LATW, page 1-6. IEEE, (2014)Voltage Regulation System for UHF RFID Tags., , , , and . SBCCI, page 1-6. IEEE, (2013)TCAD analysis and modeling for NBTI mechanism in FinFET transistors., , , and . IEICE Electronic Express, 15 (14): 20180502 (2018)Screening small-delay defects using inter-path correlation to reduce reliability risk., , and . Microelectronics Reliability, 55 (6): 1005-1011 (2015)Small-delay defects detection under process variation using Inter-Path Correlation., , , and . VTS, page 127-132. IEEE Computer Society, (2012)Voltage Regulation System for UHF RFID Tags., , , , and . SBCCI, page 1-6. IEEE, (2013)Low VDD and body bias conditions for testing bridge defects in the presence of process variations., , , and . Microelectronics Journal, 46 (5): 398-403 (2015)Computing the Detection Probability for Small Delay Defects of Nanometer ICs., and . J. Electronic Testing, 27 (6): 741-752 (2011)Computing the detection of Small Delay Defects caused by resistive opens of nanometer ICs., and . European Test Symposium, page 126-131. IEEE Computer Society, (2010)