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A Solid-State Neuron for Spiking Neural Network Implementation.

, , , , and . Engineering Letters, 16 (1): 83-89 (2008)

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Investigating Power Reduction for NoC-Based Spiking Neural Network Platforms using Channel Encoding., , , and . IJARAS, 3 (4): 1-16 (2012)Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Network Hardware Implementations., , , , , , and . IEEE Trans. Parallel Distrib. Syst., 24 (12): 2451-2461 (2013)Modular Neural Tile Architecture for Compact Embedded Hardware Spiking Neural Network., , , , , , , , and . Neural Processing Letters, 38 (2): 131-153 (2013)Evaluating the generalisation capability of a CMOS based synapse., , , , , , , and . Neurocomputing, (2012)Neuro inspired reconfigurable architecture for hardware/software co-design., , , and . SoCC, page 287-290. IEEE, (2009)A Solid-State Neuron for Spiking Neural Network Implementation., , , , and . Engineering Letters, 16 (1): 83-89 (2008)A Biologically Plausible Neuron Circuit., , , , and . IJCNN, page 715-719. IEEE, (2007)A programmable facilitating synapse device., , , and . IJCNN, page 1615-1620. IEEE, (2008)Inter-Neuron Communications for Large-Scale Neural Networks using Capacitive Coupling., , , , , , and . IJCNN, page 2779-2784. IEEE, (2006)A Spiking Neural Network Model of the Medial Superior Olive Using Spike Timing Dependent Plasticity for Sound Localization., , , , and . Front. Comput. Neurosci., (2010)