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Disambiguation of "Pasricha, Sudeep"

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Enabling heterogeneous cycle-based and event-driven simulation in a design flow integrated using the SPIRIT consortium specifications.

, , , , , , , and . Design Autom. for Emb. Sys., 11 (2-3): 119-140 (2007)

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Other publications of authors with the same name

AURA: An application and user interaction aware middleware framework for energy optimization in mobile devices., , and . ICCD, page 168-174. IEEE Computer Society, (2011)Utility Driven Dynamic Resource Management in an Oversubscribed Energy-Constrained Heterogeneous System., , , , , , , , , and . IPDPS Workshops, page 58-67. IEEE Computer Society, (2014)Stochastically robust static resource allocation for energy minimization with a makespan constraint in a heterogeneous computing environment., , , , , , , , , and 1 other author(s). AICCSA, page 22-31. IEEE Computer Society, (2011)A co-synthesis methodology for power delivery and data interconnection networks in 3D ICs., and . ISQED, page 73-79. IEEE, (2013)Thermal-aware semi-dynamic power management for multicore systems with energy harvesting., and . ISQED, page 619-626. IEEE, (2013)Energy cost optimization for geographically distributed heterogeneous data centers., , , , and . IGSC, page 1-6. IEEE Computer Society, (2015)NS-FTR: A fault tolerant routing scheme for networks on chip with permanent and runtime intermittent faults., and . ASP-DAC, page 443-448. IEEE, (2011)A novel 3D graphics DRAM architecture for high-performance and low-energy memory accesses., and . ICCD, page 467-470. IEEE Computer Society, (2015)FABSYN: floorplan-aware bus architecture synthesis., , , and . IEEE Trans. VLSI Syst., 14 (3): 241-253 (2006)CAPPS: A Framework for Power-Performance Tradeoffs in Bus-Matrix-Based On-Chip Communication Architecture Synthesis., , , and . IEEE Trans. VLSI Syst., 18 (2): 209-221 (2010)