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Run and be safe: mixed-criticality scheduling with temporary processor speedup.

, , , and . DATE, page 1329-1334. ACM, (2015)

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Minimising Access Conflicts on Shared Multi-Bank Memory., , , and . ACM Trans. Embedded Comput. Syst., 16 (5s): 135:1-135:20 (2017)Demo: Building Reliable Wireless Embedded Platforms using the Bolt Processor Interconnect., , , , , , , , and . SenSys, page 461-462. ACM, (2015)Exploring Energy Saving for Mixed-Criticality Systems on Multi-Cores., , , , and . RTAS, page 135-146. IEEE Computer Society, (2016)Bolt: A Stateful Processor Interconnect., , , , , , , , and . SenSys, page 267-280. ACM, (2015)Virtualizing Embedded Firmware to Boost Innovation Cycles., , , and . ICSA Companion, page 218-225. IEEE, (2019)Mapping mixed-criticality applications on multi-core architectures., , , and . DATE, page 1-6. European Design and Automation Association, (2014)Computing a language-based guarantee for timing properties of cyber-physical systems., , , and . DATE, page 1-6. European Design and Automation Association, (2014)Implementation of Partitioned Mixed-Criticality Scheduling on a Multi-Core Platform., , , and . ACM Trans. Embedded Comput. Syst., 16 (5s): 122:1-122:21 (2017)Service adaptions for mixed-criticality systems., , , and . ASP-DAC, page 125-130. IEEE, (2014)An Isolation Scheduling Model for Multicores., , , , and . RTSS, page 141-152. IEEE Computer Society, (2015)