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A Multibit Delta-Sigma D/A Converter Using a Charge Integrating Sub-Converter., , , , and . ISCAS, page 319-322. IEEE, (1994)An image resolution enhancing technique using adaptive sub-pixel interpolation for digital still camera system., and . IEEE Trans. Consumer Electronics, 45 (1): 118-123 (1999)A partially switched-opamp technique for high-speed low-power pipelined analog-to-digital converters., , and . IEEE Trans. on Circuits and Systems, 53-I (4): 795-801 (2006)A load-adaptive, low switching-noise data output buffer., , , , , and . ISCAS (1), page 39-42. IEEE, (1999)A 2.8Gb/s All-Digital CDR with a 10b Monotonic DCO., , , , and . ISSCC, page 222-598. IEEE, (2007)A ±1.5V 4MHz Low-Pass Gm-C Filter in CMOS., and . ASP-DAC, page 341-342. IEEE, (1998)Design of a 1.8 GHz low-noise amplifier for RF front-end in a 0.8 μm CMOS technology., and . IEEE Trans. Consumer Electronics, 47 (1): 10-15 (2001)A 0.25-µm CMOS 1.9-GHz PHS RF Transceiver With a 150-kHz Low-IF Architecture., , , , , , , and . J. Solid-State Circuits, 42 (6): 1318-1327 (2007)A Semi-Digital Delay Locked Loop for Clock Skew Minimization., , and . VLSI Design, page 584-588. IEEE Computer Society, (1999)A process and environment tolerant 3V, 2 GHz VCO with 0.8 μm CMOS technology., , , , and . IEEE Trans. Consumer Electronics, 45 (1): 171-175 (1999)