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System-Level Sub-20 nm Planar and FinFET CMOS Delay Modelling for Supply and Threshold Voltage Scaling Under Process Variation.

S. Majzoub, M. Taouil, and S. Hamdioui. J. Low Power Electronics, 15 (1): 1-10 (2019)

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A defect-oriented test approach using on-Chip current sensors for resistive defects in FinFET SRAMs.G. Medeiros, L. Bolzani, M. Taouil, F. Vargas, and S. Hamdioui. Microelectronics Reliability, (2018)On resistive open defect detection in DRAMs: The charge accumulation effect.Y. Sfikas, Y. Tsiatouhas, M. Taouil, and S. Hamdioui. ETS, page 1-6. IEEE, (2015)Quality versus cost analysis for 3D Stacked ICs.M. Taouil, S. Hamdioui, and E. Marinissen. VTS, page 1-6. IEEE Computer Society, (2014)Computation-in-memory based parallel adder.H. Nguyen, L. Xie, M. Taouil, R. Nane, S. Hamdioui, and K. Bertels. NANOARCH, page 57-62. IEEE Computer Society, (2015)Memristive Devices for Computation-In-Memory.J. Yu, H. Nguyen, L. Xie, M. Taouil, and S. Hamdioui. CoRR, (2019)Memristive devices for computation-in-memory.J. Yu, H. Nguyen, L. Xie, M. Taouil, and S. Hamdioui. DATE, page 1646-1651. IEEE, (2018)Pinhole Defect Characterization and Fault Modeling for STT-MRAM Testing.L. Wu, S. Rao, G. Medeiros, M. Taouil, E. Marinissen, F. Yasin, S. Couet, S. Hamdioui, and G. Kar. ETS, page 1-6. IEEE, (2019)RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems.M. Jenihhin, S. Hamdioui, M. Reorda, M. Krstic, P. Langendörfer, C. Sauer, A. Klotz, M. Hübner, J. Nolte, H. Vierhaus and 8 other author(s). CoRR, (2019)Device Aging : A Reliability and Security ConcernD. Kraak, M. Taouil, S. Hamdioui, P. Weckx, F. Catthoor, A. Chatterjee, A. Singh, H. Wunderlich, and N. Karimi. 2018 23RD IEEE European Test Symposium (ETS), IEEE, (2018)Exploring test opportunities for memory and interconnects in 3D ICs.M. Taouil, M. Lefter, and S. Hamdioui. IDT, page 1-6. IEEE, (2013)

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System-Level Sub-20 nm Planar and FinFET CMOS Delay Modelling for Supply and Threshold Voltage Scaling Under Process Variation.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML System-Level Sub-20 nm Planar and FinFET CMOS Delay Modelling for Supply and Threshold Voltage Scaling Under Process Variation.

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System-Level Sub-20 nm Planar and FinFET CMOS Delay Modelling for Supply and Threshold Voltage Scaling Under Process Variation.