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Disambiguation of "Dahir, Nizar"

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Thermal Optimization in Network-on-Chip-Based 3D Chip Multiprocessors Using Dynamic Programming Networks.

, , , and . ACM Trans. Embedded Comput. Syst., 13 (4s): 139:1-139:25 (2014)

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Other publications of authors with the same name

Dynamic programming-based runtime thermal management (DPRTM): An online thermal control strategy for 3D-NoC systems., , , , and . ACM Trans. Design Autom. Electr. Syst., 19 (1): 2:1-2:27 (2013)Design and Implementation of Dynamic Thermal-Adaptive Routing Strategy for Networks-on-Chip., , , , and . PDP, page 384-391. IEEE Computer Society, (2014)Network-on-Chip Multicast Architectures Using Hybrid Wire and Surface-Wave Interconnects., , , , , and . IEEE Trans. Emerging Topics Comput., 6 (3): 357-369 (2018)Characterisation of feasibility regions in FPGAs under adaptive DVFS., , , , and . FPL, page 1-4. IEEE, (2015)Highly adaptive and deadlock-free routing for three-dimensional networks-on-chip., , , and . IET Computers & Digital Techniques, 7 (6): 255-263 (2013)Modeling and Tools for Power Supply Variations Analysis in Networks-on-Chip., , , and . IEEE Trans. Computers, 63 (3): 679-690 (2014)Communication centric on-chip power grid models for networks-on-chip., , and . VLSI-SoC, page 180-183. IEEE, (2011)XL-STaGe: A cross-layer scalable tool for graph generation, evaluation and implementation., , , , , and . SAMOS, page 354-359. IEEE, (2016)Minimizing power supply noise through harmonic mappings in networks-on-chip., , , and . CODES+ISSS, page 113-122. ACM, (2012)Deadlock-free and plane-balanced adaptive routing for 3D networks-on-chip., , , , and . NoCArc@MICRO, page 31-36. ACM, (2012)