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Two-Level Main Memory Co-Design: Multi-threaded Algorithmic Primitives, Analysis, and Simulation.

, , , , , , , , , and . IPDPS, page 835-846. IEEE Computer Society, (2015)

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Enhancing NIC Performance for MPI using Processing-in-Memory., , , and . IPDPS, IEEE Computer Society, (2005)Simulating Red Storm: Challenges and Successes in Building a System Simulation., , and . IPDPS, page 1-10. IEEE, (2007)Implications of a PIM Architectural Model for MPI., , , , , and . CLUSTER, page 259-. IEEE Computer Society, (2003)Fine-Grained Message Pipelining for Improved MPI Performance., , , and . CLUSTER, IEEE Computer Society, (2006)On the Path to Exascale., , , , , , , , , and 3 other author(s). IJDST, 1 (2): 1-22 (2010)Performance analysis for using non-volatile memory DIMMs: opportunities and challenges., , , , , and . MEMSYS, page 411-420. ACM, (2017)Low Latency, High Bisection-Bandwidth Networks for Exascale Memory Systems., , , , , , , , , and 1 other author(s). MEMSYS, page 62-73. ACM, (2016)SST: A Scalable Parallel Framework for Architecture-Level Performance, Power, Area and Thermal Simulation., , , , and . Comput. J., 55 (2): 181-191 (2012)A Hardware Acceleration Unit for MPI Queue Processing., , , , and . IPDPS, IEEE Computer Society, (2005)Design Methodology for Optimizing Optical Interconnection Networks in High Performance Systems., , , , and . ISC, volume 9137 of Lecture Notes in Computer Science, page 454-471. Springer, (2015)