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Disambiguation of "Sapatnekar, Sachin S."

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Advanced spintronic memory and logic for non-volatile processors.

, , , , , , , , and . DATE, page 972-977. IEEE, (2017)

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S. Schumann

S. Seemann

S. Wartzack

Boettinger S

S. Toro

 

Other publications of authors with the same name

High Performance CMOS Macromodule Layout Synthesis., , and . ISCAS, page 179-182. IEEE, (1994)An Efficient Algorithm for Calculating the Worst-case Delay due to Crosstalk., and . ICCD, page 76-. IEEE Computer Society, (2003)Adapting to the times review of Adaptive Techniques for Dynamic Processor Optimization: Theory and Practice (Wang, A. and Naffziger, S., Eds.; 2008).. IEEE Design & Test of Computers, 25 (5): 496-497 (2008)Book Reviews: Plumbing the Depths of Leakage.. IEEE Design & Test of Computers, 23 (4): 318-319 (2006)DAC Highlights., and . IEEE Design & Test of Computers, 23 (3): 182-184 (2006)Designing "Vary" Good Circuitry.. IEEE Design & Test of Computers, 22 (6): 596-597 (2005)Power Grid Analysis.. Encyclopedia of Algorithms, (2016)Physical Design for Three-Dimensional Circuits., and . Handbook of Algorithms for Physical Design Automation, Auerbach Publications, (2008)A fast global gate collapsing technique for high performance designs using static CMOS and pass transistor logic., , and . ICCD, page 276-281. (1998)Capturing the Effect of Crosstalk on Delay.. VLSI Design, page 364-369. IEEE Computer Society, (2000)