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An Access-Pattern-Aware On-Chip Vector Memory System with Automatic Loading for SIMD Architectures.

T. Geng, E. Diken, T. Wang, L. Józwiak, and M. Herbordt. HPEC, page 1-7. IEEE, (2018)

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Dr. Jianpei Geng University of Stuttgart

Vinh Tong University of Stuttgart

Other publications of authors with the same name

A Framework for Acceleration of CNN Training on Deeply-Pipelined FPGA Clusters with Work and Weight Load Balancing.T. Geng, T. Wang, A. Sanaullah, C. Yang, R. Patel, and M. Herbordt. FPL, page 394-398. IEEE Computer Society, (2018)Fully integrated FPGA molecular dynamics simulations.C. Yang, T. Geng, T. Wang, R. Patel, Q. Xiong, A. Sanaullah, C. Wu, J. Sheng, C. Lin, V. Sachdeva and 2 other author(s). SC, page 67:1-67:31. ACM, (2019)Reconfigurable switches for high performance and flexible MPI collectives.P. Haghi, A. Guo, Q. Xiong, C. Yang, T. Geng, J. Broaddus, R. Marshall, D. Schafer, A. Skjellum, and M. Herbordt. Concurr. Comput. Pract. Exp., (2022)A Scalable Framework for Acceleration of CNN Training on Deeply-Pipelined FPGA Clusters with Weight and Workload Balancing.T. Geng, T. Wang, A. Li, X. Jin, and M. Herbordt. CoRR, (2019)GhostSZ: A Transparent FPGA-Accelerated Lossy Compression Framework.Q. Xiong, R. Patel, C. Yang, T. Geng, A. Skjellum, and M. Herbordt. FCCM, page 258-266. IEEE, (2019)Molecular Dynamics Range-Limited Force Evaluation Optimized for FPGAs.C. Yang, T. Geng, T. Wang, C. Lin, J. Sheng, V. Sachdeva, W. Sherman, and M. Herbordt. ASAP, page 263-271. IEEE, (2019)An Access-Pattern-Aware On-Chip Vector Memory System with Automatic Loading for SIMD Architectures.T. Geng, E. Diken, T. Wang, L. Józwiak, and M. Herbordt. HPEC, page 1-7. IEEE, (2018)BSTC: a novel binarized-soft-tensor-core design for accelerating bit-based approximated neural nets.A. Li, T. Geng, T. Wang, M. Herbordt, S. Song, and K. Barker. SC, page 38:1-38:30. ACM, (2019)A Survey: Handling Irregularities in Neural Network Acceleration with FPGAs.T. Geng, C. Wu, C. Tan, C. Xie, A. Guo, P. Haghi, S. He, J. Li, M. Herbordt, and A. Li. HPEC, page 1-8. IEEE, (2021)LP-BNN: Ultra-low-Latency BNN Inference with Layer Parallelism.T. Geng, T. Wang, C. Wu, C. Yang, S. Song, A. Li, and M. Herbordt. ASAP, page 9-16. IEEE, (2019)

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Disambiguation of "Geng, Tong"

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An Access-Pattern-Aware On-Chip Vector Memory System with Automatic Loading for SIMD Architectures.

Please choose a person to relate this publication to

Dr. Jianpei Geng University of Stuttgart

Vinh Tong University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Geng, Tong"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML An Access-Pattern-Aware On-Chip Vector Memory System with Automatic Loading for SIMD Architectures.

Please choose a person to relate this publication to

Dr. Jianpei Geng University of Stuttgart

Vinh Tong University of Stuttgart

Other publications of authors with the same name

Disambiguation

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URL
DOI
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Chicago
DIN 1505
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An Access-Pattern-Aware On-Chip Vector Memory System with Automatic Loading for SIMD Architectures.