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Parallelizing the FPGA global routing algorithm on multi-core systems without quality degradation., and . IEICE Electronic Express, 8 (24): 2061-2067 (2011)Efficient Host-Independent Coprocessor Architecture for Speech Coding Algorithms., , , , and . DSD, page 227-230. IEEE Computer Society, (2005)Feasibility Study of Using the RF Interconnects in Large FPGAs to Improve Routing Tracks Usage., , , and . ISVLSI, page 1-6. IEEE Computer Society, (2011)Multiplexed switch box architecture in three-dimensional FPGAs to reduce silicon area and improve TSV usage., and . ACM Great Lakes Symposium on VLSI, page 303-306. ACM, (2012)Improved performance and yield with chip master planning design methodology., and . ACM Great Lakes Symposium on VLSI, page 185-190. ACM, (2009)DENA: A Configurable Microarchitecture and Design Flow for Biomedical DNA-Based Logic Design., and . IEEE Trans. Biomed. Circuits and Systems, 11 (5): 1077-1086 (2017)Performance Improvement and Congestion Reduction of Large FPGAs Using On-Chip Microwave Interconnects., , and . IEICE Transactions, 95-C (10): 1610-1619 (2012)Layout Vulnerability Reduction against Trojan Insertion Using Security-Aware White Space Distribution., and . ISVLSI, page 551-555. IEEE Computer Society, (2017)Prediction and reduction of routing congestion., , and . ISPD, page 72-77. ACM, (2006)Improved CMOS (4; 2) compressor designs for parallel multipliers., , and . Computers & Electrical Engineering, 38 (6): 1703-1716 (2012)