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Using power gating techniques in area-array SoC floorplan design.

C. Yeh, H. Chen, L. Huang, W. Wei, C. Lu, and C. Liu. SoCC, page 233-236. IEEE, (2007)

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Dexing Liu University of Stuttgart

Jan Liu University of Stuttgart

M.Sc. Zhuoran Liu University of Stuttgart

Yanchao Liu University of Stuttgart

Shuang Liu University of Stuttgart

Other publications of authors with the same name

An Efficient Approach to Build Accurate Behavioral Models of PLL Designs.C. Kuo, Y. Wang, and C. Liu. IEICE Transactions, 89-A (2): 391-398 (2006)Levelized High-Level Current Model of Logic Blocks for Dynamic Supply Noise Analysis.M. Lee, W. Liao, and C. Liu. IEEE Trans. on CAD of Integrated Circuits and Systems, 31 (6): 845-857 (2012)Peak wake-up current estimation at gate-level with standard library information.M. Lee, Y. Liu, W. Wu, and C. Liu. VLSI-DAT, page 1-4. IEEE, (2012)Simultaneous optimization for low dropout regulator and its error amplifier with process variation.Y. Chen, G. Chu, Y. Lien, C. Lee, and C. Liu. VLSI-DAT, page 1-4. IEEE, (2014)A novel design space reduction method for efficient simulation-based optimization.H. Tseng, S. Wang, J. Chen, and C. Liu. ISCAS, page 381-384. IEEE, (2014)ILP-based inter-die routing for 3D ICs.C. Chang, P. Huang, T. Chen, and C. Liu. ASP-DAC, page 330-335. IEEE, (2011)On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design.C. Lu, H. Chen, and C. Liu. ASP-DAC, page 792-797. IEEE Computer Society, (2007)Dynamic IR drop estimation at gate level with standard library information.M. Lee, K. Lai, C. Hsu, and C. Liu. ISCAS, page 2606-2609. IEEE, (2010)A novel approach for high-level power modeling of sequential circuits using recurrent neural networks.W. Hsieh, C. Shiue, and C. Liu. ISCAS (4), page 3591-3594. IEEE, (2005)A fast heuristic approach for parametric yield enhancement of analog designs.C. Liu, Y. Chen, C. Kuo, and I. Tsai. ACM Trans. Design Autom. Electr. Syst., 17 (3): 35:1-35:20 (2012)

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Disambiguation of "Liu, Chien-Nan Jimmy"

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Using power gating techniques in area-array SoC floorplan design.

Please choose a person to relate this publication to

Dexing Liu University of Stuttgart

Jan Liu University of Stuttgart

M.Sc. Zhuoran Liu University of Stuttgart

Yanchao Liu University of Stuttgart

Shuang Liu University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Liu, Chien-Nan Jimmy"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Using power gating techniques in area-array SoC floorplan design.

Please choose a person to relate this publication to

Dexing Liu University of Stuttgart

Jan Liu University of Stuttgart

M.Sc. Zhuoran Liu University of Stuttgart

Yanchao Liu University of Stuttgart

Shuang Liu University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Using power gating techniques in area-array SoC floorplan design.