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Disambiguation of "Miyashita, Daisuke"

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A phase noise minimization of CMOS VCOs over wide tuning range and large PVT variations.

, , , , , , and . CICC, page 583-586. IEEE, (2005)

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A 0.6V 380µW -14dBm LO-input 2.4GHz double-balanced current-reusing single-gate CMOS mixer with cyclic passive combiner., , and . ISSCC, page 224-225. IEEE, (2009)Convolutional Neural Networks using Logarithmic Data Representation., , and . CoRR, (2016)A -70dBm-sensitivity 522Mbps 0.19nJ/bit-TX 0.43nJ/bit-RX transceiver for TransferJet™ SoC in 65nm CMOS., , , , , , , , , and 8 other author(s). VLSIC, page 74-75. IEEE, (2012)A Fully Integrated 2 ˟ 1 Dual-Band Direct-Conversion Mobile WiMAX Transceiver With Dual-Mode Fractional Divider and Noise-Shaping Transimpedance Amplifier in 65 nm CMOS., , , , , , , , , and 3 other author(s). J. Solid-State Circuits, 45 (12): 2774-2784 (2010)A-104 dBc/Hz In-Band Phase Noise 3 GHz All Digital PLL with Phase Interpolation Based Hierarchical Time to Digital Converter., , , , , and . IEICE Transactions, 95-C (6): 1008-1016 (2012)Post Training Weight Compression with Distribution-based Filter-wise Quantization Step., , , and . COOL CHIPS, page 1-3. IEEE, (2019)Mixed-signal circuits for embedded machine-learning applications., , , , and . ACSSC, page 1341-1345. IEEE, (2015)A 12.8-Gb/s Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth, Large-Capacity Storage Systems., , , , , , , , and . J. Solid-State Circuits, 54 (4): 1086-1095 (2019)A 12.8 GB/S Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth and Large-Capacity Storage Systems., , , , , , , and . VLSI Circuits, page 149-150. IEEE, (2018)Live Demonstration: FPGA-Based CNN Accelerator with Filter-Wise-Optimized Bit Precision., , , , , and . ISCAS, page 1. IEEE, (2019)