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Disambiguation of "Shibata, Tsugumichi"

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A 24-Gsps 3-Bit Nyquist ADC Using InP HBTs for DSP-Based Electronic Dispersion Compensation.

, , , , , , , and . IEICE Transactions, 88-C (6): 1225-1232 (2005)

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Other publications of authors with the same name

Energy-Efficient Frame-Buffer Architecture and It's Control Schemes for ONU Power Reduction., , , , , and . GLOBECOM, page 1-5. IEEE, (2011)An FPGA Implementation of the Two-Dimensional FDTD Method and Its Performance Comparison with GPGPU., , , , , , and . IEICE Transactions, 97-C (7): 697-706 (2014)A 720µW 77.93dB SNDR ΔΣ AD Modulator Using Dynamic Analog Components With Simplified Operation Phase., , and . ISPACS, page 442-446. IEEE, (2018)A reliable procedure in a new power management technique for a 200-Gbps packet forwarding LSI., , , , , , , and . IEICE Electronic Express, 10 (11): 20130231 (2013)Extendable point-to-multi-point protocol processor for 10G-EPON MAC SoCs., , , , , , and . ISCAS, page 1464-1467. IEEE, (2012)A 2nd-order Delta Sigma AD modulator using dynamic amplifier and dynamic SAR quantizer., , and . ISPACS, page 1-5. IEEE, (2016)A 24-Gsps 3-Bit Nyquist ADC Using InP HBTs for DSP-Based Electronic Dispersion Compensation., , , , , , , and . IEICE Transactions, 88-C (6): 1225-1232 (2005)An FPGA implementation of 3D numerical simulations on a 2D SIMD array processor., , , and . ISCAS, page 938-941. IEEE, (2015)An Injection-Controlled 10-Gb/s Burst-Mode CDR Circuit for a 1G/10G PON System., , , , , and . IEICE Transactions, 94-C (4): 582-588 (2011)Software-Hardware-Cooperative Protocol Processor for Extendable 10G-EPON MAC Chip., , , , , , , and . IEICE Transactions, 98-C (1): 45-52 (2015)