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Disambiguation of "Kurdahi, Fadi J."

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Circuit Inspired Modeling Method for Irrigation.

, , , and . DSD, page 328-335. IEEE Computer Society, (2018)

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J. K\"astner

J. Schwarz

J. K\"astner

J Walter

J. Vogel

 

Other publications of authors with the same name

Layout-Driven RTL Binding Techniques for High-Level Synthesis., and . ISSS, page 33-38. ACM / IEEE Computer Society, (1996)Cross-Layer Approaches to Designing Reliable Systems Using Unreliable Chips., , , and . VLSI Design, page 14-15. IEEE Computer Society, (2008)Process Variation Aware SRAM/Cache for aggressive voltage-frequency scaling., , , and . DATE, page 911-916. IEEE, (2009)Incorporating the Controller Effects During Register Transfer Level Synthesis., and . EDAC-ETC-EUROASIC, page 308-313. IEEE Computer Society, (1994)Optimal Recovery Point Insertion for High-Level Synthesis of Recoverable Microarchitectures., , and . FTCS, page 50-59. IEEE Computer Society, (1995)Inquisitive Defect Cache: A Means of Combating Manufacturing Induced Process Variation., , , and . IEEE Trans. VLSI Syst., 19 (9): 1597-1609 (2011)Evaluating Carbon Nanotube Global Interconnects for Chip Multiprocessor Applications., , and . IEEE Trans. VLSI Syst., 18 (9): 1376-1380 (2010)Accurate prediction of quality metrics for logic level designs targeted toward lookup-table-based FPGAs., and . IEEE Trans. VLSI Syst., 7 (4): 411-418 (1999)A Low Power JPEG2000 Encoder With Iterative and Fault Tolerant Error Concealment., , , and . IEEE Trans. VLSI Syst., 17 (6): 827-837 (2009)AS8-static random access memory (SRAM): asymmetric SRAM architecture for soft error hardening enhancement., , , , and . IET Circuits, Devices & Systems, 11 (1): 89-94 (2017)