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Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System.

, , , , , , and . VLSI Signal Processing, 28 (1-2): 47-61 (2001)

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Design and implementation of the 'Tiny RISC' microprocessor., , , , , and . Microprocessors and Microsystems - Embedded Hardware Design, 16 (4): 187-193 (1992)Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System., , , , , , and . VLSI Signal Processing, 28 (1-2): 47-61 (2001)Evaluation of a Low-Power Reconfigurable DSP Architecture., , , , and . IPPS/SPDP Workshops, volume 1388 of Lecture Notes in Computer Science, page 55-60. Springer, (1998)Special Features of a VLIW Architecture., and . IPPS, page 224-227. IEEE Computer Society, (1991)Pipelining and bypassing in a VLIW processor., and . ISCA, page 434. ACM, (1992)Pipelining and Bypassing in a VLIW Processor., and . IEEE Trans. Parallel Distrib. Syst., 5 (6): 658-664 (1994)A Percolation Based VLIW Architecture., , , and . ICPP (1), page 144-148. CRC Press, (1991)