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Design Space Exploration for 3-D Cache., , , , and . IEEE Trans. VLSI Syst., 16 (4): 444-455 (2008)Exploration of Electrical and Novel Optical Chip-to-Chip Interconnects., , , , , , and . IEEE Design & Test, 31 (5): 28-35 (2014)Temperature-Aware Task Allocation and Scheduling for Embedded Multiprocessor Systems-on-Chip (MPSoC) Design., and . VLSI Signal Processing, 45 (3): 177-189 (2006)Reliability Concerns in Embedded System Designs., and . IEEE Computer, 39 (1): 118-120 (2006)Thermal-aware P/G TSV planning for IR drop reduction in 3D ICs., , , , , and . Integration, 46 (1): 1-9 (2013)Fabrication Cost Analysis and Cost-Aware Design Space Exploration for 3-D ICs., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 29 (12): 1959-1972 (2010)Architecting Microprocessor Components in 3D Design Space., , , , , and . VLSI Design, page 103-108. IEEE Computer Society, (2007)MAGE: adaptive granularity and ECC for resilient and power efficient memory systems., , , , , , , and . SC, page 33. IEEE/ACM, (2012)Designing vertical bandwidth reconfigurable 3D NoCs for many core systems., , , , and . 3DIC, page 1-7. IEEE, (2014)An ILP Formulation for Reliability-Oriented High-Level Synthesis., , , , , , and . ISQED, page 364-369. IEEE Computer Society, (2005)