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Selective Body Biasing for Post-Silicon Tuning of Sub-Threshold Designs: An Adaptive Filtering Approach.

H. Geng, J. Liu, P. Luo, L. Cheng, S. Grant, and Y. Shi. IEEE Trans. on CAD of Integrated Circuits and Systems, 34 (5): 713-725 (2015)

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Xiaoyu Cheng University of Stuttgart

Tiffany Cheng University of Stuttgart

Univ. -Prof. Dr. Po Wen Cheng University of Stuttgart

Yingxing Cheng University of Stuttgart

Cheng-I Ho University of Stuttgart

Other publications of authors with the same name

Selective body biasing for post-silicon tuning of sub-threshold designs: A semi-infinite programming approach with Incremental Hypercubic Sampling.H. Geng, J. Liu, J. Liu, P. Luo, L. Cheng, S. Grant, and Y. Shi. Integration, (2016)Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits.P. Luo, J. Chen, C. Wey, L. Cheng, J. Chen, and W. Wu. IEEE Trans. on CAD of Integrated Circuits and Systems, 27 (11): 2097-2101 (2008)Power delivery network design for wiring and TSV resource minimization in TSV-based 3-D ICs.S. Wei, Y. Lee, C. Ho, C. Sun, and L. Cheng. VLSI-DAT, page 1-4. IEEE, (2013)Benchmarking for research in power delivery networks of three-dimensional integrated circuits.P. Luo, C. Zhang, Y. Chang, L. Cheng, H. Lee, B. Sheu, Y. Su, D. Kwai, and Y. Shi. ISPD, page 17-24. ACM, (2013)Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells.S. Luo, K. Chang, M. Chen, C. Huang, Y. Chiu, P. Chen, L. Cheng, C. Liu, and Y. Chu. IEEE Trans. on Circuits and Systems, 61-II (12): 947-951 (2014)Methodology of exploring ESL/RTL many-core platforms for developing embedded parallel applications.J. Lai, C. Huang, T. Hsu, J. Liou, T. Yeh, L. Cheng, and J. Lu. SoCC, page 286-291. IEEE, (2014)A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS.T. Lin, C. Chien, P. Chang, C. Chen, P. Wang, T. Shyu, C. Chou, S. Luo, J. Guo, T. Chen and 8 other author(s). ISSCC, page 158-159. IEEE, (2013)Reliable Power Delivery System Design for Three-Dimensional Integrated Circuits (3D ICs).P. Luo, T. Wang, C. Wey, L. Cheng, B. Sheu, and Y. Shi. ISVLSI, page 356-361. IEEE Computer Society, (2012)Capturing the phantom of the power grid - on the runtime adaptive techniques for noise reduction.T. Wang, P. Luo, Y. Su, L. Cheng, D. Kwai, and Y. Shi. ASP-DAC, page 640-645. IEEE, (2012)Cost-Effective TAP-Controlled Serialized Compressed Scan Architecture for 3D Stacked ICs.C. Chen, Y. Chen, C. Hsu, M. Wu, K. Luo, B. Bai, and L. Cheng. Asian Test Symposium, page 107-108. IEEE Computer Society, (2013)

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Disambiguation of "Cheng, Liang-Chia"

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Selective Body Biasing for Post-Silicon Tuning of Sub-Threshold Designs: An Adaptive Filtering Approach.

Please choose a person to relate this publication to

Xiaoyu Cheng University of Stuttgart

Tiffany Cheng University of Stuttgart

Univ. -Prof. Dr. Po Wen Cheng University of Stuttgart

Yingxing Cheng University of Stuttgart

Cheng-I Ho University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Cheng, Liang-Chia"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Selective Body Biasing for Post-Silicon Tuning of Sub-Threshold Designs: An Adaptive Filtering Approach.

Please choose a person to relate this publication to

Xiaoyu Cheng University of Stuttgart

Tiffany Cheng University of Stuttgart

Univ. -Prof. Dr. Po Wen Cheng University of Stuttgart

Yingxing Cheng University of Stuttgart

Cheng-I Ho University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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Selective Body Biasing for Post-Silicon Tuning of Sub-Threshold Designs: An Adaptive Filtering Approach.