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An architectural co-synthesis algorithm for energy-aware network-on-chip design.

W. Hung, Y. Chen, C. Yang, Y. Chang, and A. Su. SAC, page 680-684. ACM, (2007)

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Marlon Suditsch University of Stuttgart

A Multiscale and Multiphase Model of Function-Perfusion Growth Processes in the Human LiverL. Lambers, M. Suditsch, A. Wagner, and T. Ricken. PAMM, (January 2021)

Michaela Suttner University of Stuttgart

Abdou Suso University of Stuttgart

Andreas Sülzle University of Stuttgart

Inti Runa Supa Stölben University of Stuttgart

Other publications of authors with the same name

Transaction Level Modeling and Design Space Exploration for SOC Test Architectures.C. Chang, C. Hsiao, K. Lee, and A. Su. Asian Test Symposium, page 200-205. IEEE Computer Society, (2009)A Hybrid Multicast Routing Approach with Enhanced Methods for Mesh-Based Networks-on-Chip.C. Wu, K. Lee, and A. Su. IEEE Trans. Computers, 67 (9): 1231-1245 (2018)Flow Maximization for NoC Routing Algorithms.Y. Lan, M. Chen, A. Su, Y. Hu, and S. Chen. ISVLSI, page 335-340. IEEE Computer Society, (2008)Applying ESL in A Dual-Core SoC Platform Designing.A. Su, and R. Chen. SoCC, page 171-174. IEEE, (2006)Buffer size minimization method considering mix-clock domains and discontinuous data access.L. Chiou, L. Lu, B. Lin, and A. Su. APCCAS, page 380-383. IEEE, (2012)A practice of ESL verification methodology from SystemC to FPGA: using EPC class-1 generation-2 RFID tag design as an example.W. Young, C. Huang, A. Su, C. Jou, and F. Hsueh. ASP-DAC, page 821-824. IEEE, (2010)Low Power Heuristic Block-level Voltage/Frequency Scheduling.L. Weng, X. Wang, A. Su, and B. Liu. ESA/VLSI, page 577-581. CSREA Press, (2004)A software/hardware co-debug platform for multi-core systems.K. Lee, A. Su, L. Chen, J. Jhou, J. Kuo, and M. Liu. ASICON, page 259-262. IEEE, (2011)A low-cost SOC debug platform based on on-chip test architectures.K. Lee, S. Liang, and A. Su. SoCC, page 161-164. IEEE, (2009)Fluidity concept for NoC: A congestion avoidance and relief routing scheme.Y. Lan, M. Chen, A. Su, Y. Hu, and S. Chen. SoCC, page 65-70. IEEE, (2008)

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Disambiguation of "Su, Alan P."

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An architectural co-synthesis algorithm for energy-aware network-on-chip design.

Please choose a person to relate this publication to

Marlon Suditsch University of Stuttgart

Michaela Suttner University of Stuttgart

Abdou Suso University of Stuttgart

Andreas Sülzle University of Stuttgart

Inti Runa Supa Stölben University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Su, Alan P."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML An architectural co-synthesis algorithm for energy-aware network-on-chip design.

Please choose a person to relate this publication to

Marlon Suditsch University of Stuttgart

Michaela Suttner University of Stuttgart

Abdou Suso University of Stuttgart

Andreas Sülzle University of Stuttgart

Inti Runa Supa Stölben University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

An architectural co-synthesis algorithm for energy-aware network-on-chip design.