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Clock Distribution Networks with Gradual Signal Transition Time Relaxation for Reduced Power Consumption., and . Journal of Circuits, Systems, and Computers, 17 (6): 1173-1191 (2008)Buffer Insertion and Sizing in Clock Distribution Networks with Gradual Transition Time Relaxation for Reduced Power Consumption., and . ICECS, page 845-848. IEEE, (2007)Asymmetric dual-gate multi-fin keeper bias options and optimization for low power and robust FinFET domino logic., and . APCCAS, page 1720-1723. IEEE, (2008)Dual Supply Voltages and Dual Clock Frequencies for Lower Clock Power and Suppressed Temperature-Gradient-Induced Clock Skew., and . IEEE Trans. VLSI Syst., 18 (3): 347-355 (2010)Characterization of New Static Independent-Gate-Biased FinFET Latches and Flip-Flops under Process Variations., and . ISQED, page 311-316. IEEE Computer Society, (2008)Statistical Data Stability and Leakage Evaluation of FinFET SRAM Cells with Dynamic Threshold Voltage Tuning under Process Parameter Fluctuations., , and . ISQED, page 305-310. IEEE Computer Society, (2008)Low-Power Low-Voltage Hot-Spot Tolerant Clocking with Suppressed Skew., and . ISCAS, page 645-648. IEEE, (2007)Multi-Vth FinFET sequential circuits with independent-gate bias and work-function engineering for reduced power consumption., and . APCCAS, page 348-351. IEEE, (2008)Multi-Threshold Voltage FinFET Sequential Circuits., and . IEEE Trans. VLSI Syst., 19 (1): 151-156 (2011)Dynamic wordline voltage swing for low leakage and stable static memory banks., and . ISCAS, page 1894-1897. IEEE, (2008)