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Tackling the bottleneck of delay tables in 3D ultrasound imaging., , , , , , and . DATE, page 1683-1688. ACM, (2015)A Network Traffic Generator Model for Fast Network-on-Chip Simulation., , , , , and . DATE, page 780-785. IEEE Computer Society, (2005)A post-compiler approach to scratchpad mapping of code., , , , and . CASES, page 259-267. ACM, (2004)Towards Ultrasound Everywhere: A Portable 3D Digital Back-End Capable of Zone and Compound Imaging., , , , , , , and . IEEE Trans. Biomed. Circuits and Systems, 12 (5): 968-981 (2018)Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow., , and . Nano-Net, page 15. ICST/ACM, (2007)Simultaneous memory and bus partitioning for SoC architectures., , , , and . SoCC, page 125-128. IEEE, (2005)Synthesis of low-overhead configurable source routing tables for network interfaces., , and . DATE, page 262-267. IEEE, (2009)Contrasting a NoC and a traditional interconnect fabric with layout awareness., , , , and . DATE, page 124-129. European Design and Automation Association, Leuven, Belgium, (2006)Safe and Efficient Deployment of Data-Parallelizable Applications on Many-Core Platforms: Theory and Practice., , , and . IEEE Design & Test, 35 (4): 7-15 (2018)QoS-Driven Reconfigurable Parallel Computing for NoC-Based Clustered MPSoCs., , , , , , , and . IEEE Trans. Industrial Informatics, 9 (3): 1613-1624 (2013)