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Disambiguation of "Pradhan, Dhiraj K."

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Investigating the impact of NBTI on different power saving cache strategies.

, , , , and . DATE, page 592-597. IEEE, (2010)

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K. Stahl

K. Gaiser

K. Lindow

Grzegorz K. Karch

Dipl.-Ing. Thomas Kuestner

Scan time reduction in DWI of the pancreas using simultaneous multislice technique with different acceleration factors: how fast can we go?, , , , , , , and . Proceedings of the International Society for Magnetic Resonance in Medicine (ISMRM), Honolulu, Hawaii, USA, (April 2017)
 

Other publications of authors with the same name

DOE-ILP Based Simultaneous Power and Read Stability Optimization in Nano-CMOS SRAM., , , and . J. Low Power Electronics, 6 (3): 390-400 (2010)Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph., , , and . IEEE Trans. VLSI Syst., 19 (8): 1469-1480 (2011)Matrix Codes for Reliable and Cost Efficient Memory Chips., , and . IEEE Trans. VLSI Syst., 19 (3): 420-428 (2011)Store Address Generator with On-Line Fault-Detection Capability., , and . IEEE Trans. Computers, 26 (11): 1144-1151 (1977)The Effect of Program Behavior on Fault Observability., and . IEEE Trans. Computers, 45 (8): 868-880 (1996)Aliasing Probability for Multiple Input Signature Analyzer., , and . IEEE Trans. Computers, 39 (4): 586-591 (1990)Roll-Forward and Rollback Recovery: Performance-Reliability Trade-Off., and . IEEE Trans. Computers, 46 (3): 372-378 (1997)The De Bruijn Multiprocessor Network: A Versatile Parallel Processing and Sorting Network for VLSI., and . IEEE Trans. Computers, 38 (4): 567-581 (1989)Correction: IEEE Transactions on Computers 41(1): 122-123 (1991).A Fault Tolerant Hybrid Memory Structure and Memory Management Algorithms., and . IEEE Trans. Computers, 44 (3): 408-418 (1995)Processor Allocation in Hypercube Multicomputers: Fast and Efficient Strategies for Cubic and Noncubic Allocation., and . IEEE Trans. Parallel Distrib. Syst., 6 (10): 1108-1122 (1995)