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Time-division-multiplexed arbitration in silicon nanophotonic networks-on-chip for high-performance chip multiprocessors., , , , , , and . J. Parallel Distrib. Comput., 71 (5): 641-650 (2011)Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors., , and . IEEE Trans. Computers, 57 (9): 1246-1260 (2008)The Connection-Then-Credit Flow Control Protocol for Heterogeneous Multicore Systems-on-Chip., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 29 (6): 869-882 (2010)Topology-Based Performance Analysis and Optimization of Latency-Insensitive Systems., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 27 (12): 2277-2290 (2008)Aura II: Combining Negative Thinking and Branch-and-Bound in Unate Covering Problems., , , , and . VLSI, volume 162 of IFIP Conference Proceedings, page 346-361. Kluwer, (1999)Modeling of Substrate Noise Injected by Digital Libraries., , , , , , , and . ISQED, page 488-492. IEEE Computer Society, (2001)Platform-Based Design for Embedded Systems., , , , and . Embedded Systems Handbook, CRC Press, (2005)Efficient Synthesis of Networks On Chip., , and . ICCD, page 146-150. IEEE Computer Society, (2003)A synthesis-parameter tuning system for autonomous design-space exploration., , , , , and . DATE, page 1148-1151. IEEE, (2016)Languages and Tools for Hybrid Systems Design., , , and . Foundations and Trends in Electronic Design Automation, (2006)