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A Dynamically Reconfigurable Pattern Matcher for Regular Expressions on FPGA., , , and . PARCO, volume 22 of Advances in Parallel Computing, page 611-618. IOS Press, (2011)Reservoir-based techniques for speech recognition., , and . IJCNN, page 1050-1053. IEEE, (2006)Hamiltonian Path Strategy for Deadlock-Free and Adaptive Routing in Diametrical 2D Mesh NoCs., and . CCGRID, page 1209-1212. IEEE Computer Society, (2015)Mapping logic to reconfigurable FPGA routing., , and . FPL, page 315-321. IEEE, (2012)Towards balanced traffic distribution in NoCs using a highly adaptive path-based routing algorithm., and . HPCS, page 194-201. IEEE, (2013)Generating new benchmark designs using a multi-terminal net model., , and . Integration, 27 (2): 113-129 (1999)Special issue on System-Level Interconnect Prediction., , and . Integration, 40 (4): 381 (2007)Loop Transformations to Reduce the Dynamic FPGA Recon?guration Overhead., , , and . ReConFig, page 133-138. IEEE Computer Society, (2008)Reconfigurability-Aware Structural Mapping for LUT-Based FPGAs., and . ReConFig, page 223-228. IEEE Computer Society, (2008)An Integrated on-Silicon Verification Method for FPGA Overlays., , , and . J. Electronic Testing, 35 (2): 173-189 (2019)