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Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures., , , and . ISCA, page 97-108. IEEE Computer Society, (2014)A Fully Integrated Battery-Powered System-on-Chip in 40-nm CMOS for Closed-Loop Control of Insect-Scale Pico-Aerial Vehicle., , , , , , , , , and . J. Solid-State Circuits, 52 (9): 2374-2387 (2017)Assisting High-Level Synthesis Improve SpMV Benchmark Through Dynamic Dependence Analysis., , , , and . IEEE Trans. on Circuits and Systems, 65-II (10): 1440-1444 (2018)On-chip deep neural network storage with multi-level eNVM., , , , , and . DAC, page 169:1-169:6. ACM, (2018)MASR: A Modular Accelerator for Sparse RNNs., , , , , , , and . PACT, page 1-14. IEEE, (2019)Quantifying acceleration: Power/performance trade-offs of application kernels in hardware., , , and . ISLPED, page 395-400. IEEE, (2013)The Aladdin Approach to Accelerator Design and Modeling., , , and . IEEE Micro, 35 (3): 58-70 (2015)Minerva: Enabling Low-Power, Highly-Accurate Deep Neural Network Accelerators., , , , , , , , and . ISCA, page 267-278. IEEE Computer Society, (2016)Ares: a framework for quantifying the resilience of deep neural networks., , , , , , , and . DAC, page 17:1-17:6. ACM, (2018)Weightless: Lossy weight encoding for deep neural network compression., , , , , , and . ICLR (Workshop), OpenReview.net, (2018)