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Formal Verification of Digital Circuits Using Symbolic Ternary System Models.

, and . CAV, volume 531 of Lecture Notes in Computer Science, page 33-43. Springer, (1990)

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On the Complexity of VLSI Implementations and Graph Representations of Boolean Functions with Application to Integer Multiplication.. IEEE Trans. Computers, 40 (2): 205-213 (1991)Incorporating timing constraints in the efficient memory model for symbolic ternary simulation., and . ICCD, page 400-406. (1998)Deciding Quantifier-Free Presburger Formulas Using Parameterized Solution Bounds., and . LICS, page 100-109. IEEE Computer Society, (2004)Learning conditional abstractions., , and . FMCAD, page 116-124. FMCAD Inc., (2011)An efficient graph representation for arithmetic circuitverification., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 20 (12): 1443-1454 (2001)TLSim and EVC: a term-level symbolic simulator and an efficient decision procedure for the logic of equality with uninterpreted functions and memories., and . IJES, 1 (1/2): 134-149 (2005)SetA*: An Efficient BDD-Based Heuristic Search Algorithm., , and . AAAI/IAAI, page 668-673. AAAI Press / The MIT Press, (2002)Set Manipulation with Boolean Functional Vectors for Symbolic Reachability Analysis., and . DATE, page 10816-10821. IEEE Computer Society, (2003)Unbounded, Fully Symbolic Model Checking of Timed Automata using Boolean Methods., and . CAV, volume 2725 of Lecture Notes in Computer Science, page 154-166. Springer, (2003)System modeling and verification with UCLID.. MEMOCODE, page 3-4. IEEE Computer Society, (2004)