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Workshop Preview of the 2nd International Workshop on Software for Parallel Systems (SEPS 2015).

, , , , and . SPLASH (Companion Volume), page 95-96. ACM, (2015)

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ARV-ALA: Improving performance of software transactional memory through adaptive read and write policies., , and . Sci. Comput. Program., 78 (9): 1559-1571 (2013)Reducing Static and Dynamic Power of L1 Data Caches in GPGPUs.. IPDPS Workshops, page 798-804. IEEE Computer Society, (2014)A Power-Aware Prediction-Based Cache Coherence Protocol for Chip Multiprocessors., and . IPDPS, page 1-8. IEEE, (2007)Exploiting program cyclic behavior to reduce memory latency in embedded processors., and . SAC, page 1482-1486. ACM, (2008)Mitigating Critical Path Decompression Latency in Compressed L1 Data Caches Via Prefetching., and . IPDPS Workshops, page 694-701. IEEE Computer Society, (2018)Workshop Preview of the 2nd International Workshop on Software for Parallel Systems (SEPS 2015)., , , , and . SPLASH (Companion Volume), page 95-96. ACM, (2015)Using supplier locality in power-aware interconnects and caches in chip multiprocessors., and . Journal of Systems Architecture - Embedded Systems Design, 54 (5): 507-518 (2008)A Low Power BIST Architecture for FPGA Look-Up Table Testing., and . VLSI-SOC, page 394-397. Technische Universität Darmstadt, Insitute of Microelectronic Systems, (2003)An efficient racetrack memory for L2 cache in GPGPUs., and . Comput. Syst. Sci. Eng., (2017)Power-Aware L1 and L2 Caches for GPGPUs., and . Euro-Par, volume 8632 of Lecture Notes in Computer Science, page 354-365. Springer, (2014)