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Improved circuitry for soft error correction in combinational logic in pipelined designs.

, , , and . IOLTS, page 93-98. IEEE, (2014)

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A New Self-Checking Sum-Bit Duplicated Carry-Select Adder., , , and . DATE, page 1360-1361. IEEE Computer Society, (2004)Synthesis of Low-Cost Parity-Based Partially Self-Checking Circuits., , , and . IOLTS, page 35-. IEEE Computer Society, (2003)New Linear SEC-DED Codes with Reduced Triple Bit Error Miscorrection Probability., , and . IOLTS, page 37-42. IEEE Computer Society, (2008)A New Method for Concurrent Checking by Use of a 1-out-of-4 Code., , , and . IOLTW, page 147-152. IEEE Computer Society, (2000)Necessary and Sufficient Conditions for the Existence of Totally Self-Checking Circuits., , , and . IOLTS, page 25-30. IEEE Computer Society, (2004)Modified DEC BCH codes for parallel correction of 3-bit errors comprising a pair of adjacent errors., , and . IOLTS, page 116-121. IEEE, (2014)Self-Checking Combinational Circuits with Unidirectionally Independent Outputs., , , and . VLSI Design, 1998 (4): 333-345 (1998)Parallel matrix multiplication on an array-logical processor., , , and . Recent Issues in Pattern Analysis and Recognition, volume 399 of Lecture Notes in Computer Science, page 72-78. Springer, (1989)Memories for Parallel Subtree-Access., and . Parallel Algorithms and Architectures, volume 269 of Lecture Notes in Computer Science, page 122-130. Springer, (1987)Code disjoint self-parity combinational circuits for self-testing, concurrent fault detection and parity scan design., and . VTS, page 151-157. IEEE Computer Society, (1994)