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Robust power management in the IBM z13., , , , , , , , , and 5 other author(s). IBM Journal of Research and Development, (2015)System power management support in the IBM POWER6 microprocessor., , , , , , and . IBM Journal of Research and Development, 51 (6): 733-746 (2007)Debugging post-silicon fails in the IBM POWER8 bring-up lab., , , , , , , , , and 3 other author(s). IBM Journal of Research and Development, (2015)Active management of timing guardband to save energy in POWER7., , , , , , and . MICRO, page 1-11. ACM, (2011)26.2 Power supply noise in a 22nm z13™ microprocessor., , , , , , , , , and 5 other author(s). ISSCC, page 438-439. IEEE, (2017)Voltage droop reduction using throttling controlled by timing margin feedback., , , , , and . VLSIC, page 96-97. IEEE, (2012)A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor., , , , , , , , and . ISSCC, page 398-399. IEEE, (2007)Fault-Tolerant Design of the IBM Power6 Microprocessor., , , , , , and . IEEE Micro, 28 (2): 30-38 (2008)Fault-tolerant design of the IBM pSeries 690 system using POWER4 processor technology., , , and . IBM Journal of Research and Development, 46 (1): 77-86 (2002)Runtime power reduction capability of the IBM POWER7+ chip., , , , , , , , , and . IBM Journal of Research and Development, (2013)