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Fully Adaptive Fault-Tolerant Routing Algorithm for Network-on-Chip Architectures., , , and . DSD, page 527-534. IEEE Computer Society, (2007)Network-on-Chip Architecture Exploration Framework., , , and . DSD, page 375-382. IEEE Computer Society, (2009)Applikationsspezifische Optimierung der Kommunikation in Mehrkern-Architekturen für eingebettete Systeme.. Eberhard Karls University of Tübingen, (2013)Formal performance analysis and simulation of UML/SysML models for ESL design., , , and . DATE, page 242-247. European Design and Automation Association, Leuven, Belgium, (2006)Latency-Optimized Force-directed Process Mapping for MPSoC Architectures., , , and . MBMV, page 145-156. Verlag Dr. Kovac, (2012)Stereo depth map computation on a Tilera TILEPro64 embedded multicore processor., , , , , and . DASIP, page 1-2. IEEE, (2012)Shared memory aware MPSoC software deployment., , , and . DATE, page 1771-1776. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Distance-Constrained Force-Directed Process Mapping for MPSoC Architectures., , , and . DSD, page 592-599. IEEE Computer Society, (2012)Parallel matching-based estimation - a case study on three different hardware architectures., , and . Intelligent Vehicles Symposium, page 1060-1067. IEEE, (2011)Optimized software mapping for advanced driver assistance systems., , , and . SIES, page 181-190. IEEE, (2012)