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Disambiguation of "Soudris, Dimitrios"

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Systematic Exploration of Power-Aware Scenarios for IEEE 802.11ac WLAN Systems.

, , , , and . DSD, page 28-35. IEEE Computer Society, (2014)

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Dimitrios Tsoutsoulopoulos University of Stuttgart

Dimitrios Thalassinos University of Stuttgart

 

Other publications of authors with the same name

A Power-Aware Placement and Routing Algorithm Targeting 3D FPGAs., and . J. Low Power Electronics, 4 (3): 275-289 (2008)A Novel Division Algorithm and Architectures for Parallel and Sequential Processing., , , and . Journal of Circuits, Systems, and Computers, 14 (2): 281-296 (2005)A Novel Allocation Methodology for Partial and Dynamic Bitstream Generation for FPGA Architectures., , and . Journal of Circuits, Systems, and Computers, 19 (3): 701-717 (2010)Memory power optimization of hardware implementations of multimedia applications onto FPGA platforms., , and . J. Embedded Computing, 1 (3): 353-362 (2005)Multiple-Valued Logic Voltage-Mode Storage Circuits Based On True-Single-Phase Clocked Logic., , , , and . Great Lakes Symposium on VLSI, page 83-88. IEEE Computer Society, (1998)A Novel Methodology for Temperature-Aware Placement and Routing of FPGAs., and . ISVLSI, page 55-60. IEEE Computer Society, (2007)Efficient High Level Synthesis Exploration Methodology Combining Exhaustive and Gradient-Based Pruned Searching., , , , and . ISVLSI, page 104-109. IEEE Computer Society, (2010)A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs., , and . DATE, page 172-177. IEEE, (2009)A divide and conquer based distributed run-time mapping methodology for many-core platforms., , , and . DATE, page 111-116. IEEE, (2012)A Code Transformation-Based Methodology for Improving I-Cache Performance of DSP Applications., , , and . DATE, page 977-983. IEEE Computer Society, (2002)