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Disambiguation of "Bayliss, Samuel"

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Compiling Higher Order Functional Programs to Composable Digital Hardware.

, , , , , , and . FCCM, page 234. IEEE Computer Society, (2014)

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Samuel Leder University of Stuttgart

Enhanced co-design and evaluation of a collective robotic construction system for the assembly of large-scale in-plane timber structures, , , and . Automation in Construction, (2024)

Samuel Morgan University of Stuttgart

Samuel Kaufmann University of Stuttgart

Samuel Pilch University of Stuttgart

Samuel Beck University of Stuttgart

 

Other publications of authors with the same name

Area implications of memory partitioning for high-level synthesis on FPGAs., , , , and . FPL, page 1-4. IEEE, (2014)Survey of domain-specific languages for FPGA computing., and . FPL, page 1-12. IEEE, (2016)Application Specific Memory Access, Reuse and Reordering for SDRAM., and . ARC, volume 6578 of Lecture Notes in Computer Science, page 41-52. Springer, (2011)High-level synthesis of dynamic data structures: A case study using Vivado HLS., , and . FPT, page 362-365. IEEE, (2013)Analytical synthesis of bandwidth-efficient SDRAM address generators., and . Microprocessors and Microsystems - Embedded Hardware Design, 36 (8): 665-675 (2012)Polyhedral-Based Dynamic Loop Pipelining for High-Level Synthesis., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 37 (9): 1802-1815 (2018)Datapath Synthesis for Overclocking: Online Arithmetic for Latency-Accuracy Trade-offs., , , , and . DAC, page 190:1-190:6. ACM, (2014)Compiling Higher Order Functional Programs to Composable Digital Hardware., , , , , , and . FCCM, page 234. IEEE Computer Society, (2014)Offline Synthesis of Online Dependence Testing: Parametric Loop Pipelining for HLS., , and . FCCM, page 159-162. IEEE Computer Society, (2015)Optimizing SDRAM bandwidth for custom FPGA loop accelerators., and . FPGA, page 195-204. ACM, (2012)