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Automist - A Tool for Automated Instruction Set Characterization of Embedded Processors.

M. Wendt, M. Grumer, C. Steger, and U. Neffe. Power-aware Computing Systems, volume 07041 of Dagstuhl Seminar Proceedings, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany, (2007)

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Hon. -Prof. Dr. Christian Steger University of Stuttgart

Christian León University of Stuttgart

Christian Hölzl University of Stuttgart

Christian Semmler University of Stuttgart

Christian Bartsch University of Stuttgart

Other publications of authors with the same name

Energy Estimation Based on Hierarchical Bus Models for Power-Aware Smart Cards.U. Neffe, K. Rothbart, C. Steger, R. Weiss, E. Rieger, and A. Mühlberger. DATE, page 300-305. IEEE Computer Society, (2004)Automatic Testbench Generation for Simulation-based Verification of Safety-critical Systems in UML.R. Weissnegger, M. Pistauer, C. Kreiner, M. Schuß, K. Römer, and C. Steger. PECCS, page 70-75. SciTePress, (2016)Power consumption profile analysis for security attack simulation in smart cards at high abstraction level.K. Rothbart, U. Neffe, C. Steger, R. Weiss, E. Rieger, and A. Mühlberger. EMSOFT, page 214-217. ACM, (2005)Horizontal and vertical HW/SW co-design flows for power aware smart card designs.M. Grumer, C. Steger, M. Wendt, A. Mühlberger, and U. Neffe. IJES, 3 (1/2): 93-106 (2007)A HW/SW Codesign Framework Based on Distributed DSP Virtual Machines.C. Kreiner, C. Steger, E. Teiniker, and R. Weiss. DSD, page 212-219. IEEE Computer Society, (2001)Case study on multiple fault dependability and security evaluations.J. Grinschgl, A. Krieg, C. Steger, R. Weiss, H. Bock, J. Haid, T. Aichinger, and C. Ulbricht. Microprocessors and Microsystems - Embedded Hardware Design, 37 (2): 218-227 (2013)Fault insertion testing of a novel CPLD-based fail-safe system.G. Grießnig, R. Mader, C. Steger, and R. Weiss. DATE, page 214-219. IEEE, (2009)System side-channel leakage emulation for HW/SW security coverification of MPSoCs.A. Krieg, J. Grinschgl, C. Steger, R. Weiss, H. Bock, and J. Haid. DDECS, page 139-144. IEEE, (2012)A defensive Java Card virtual machine to thwart fault attacks by microarchitectural support.M. Lackner, R. Berlach, M. Hraschan, R. Weiss, and C. Steger. CRiSIS, page 1-8. IEEE Computer Society, (2013)A Generic Timing Mechanism for Using the APPLES Gate-Level Simulator in a Mixed-Level Simulation Environment.A. Maili, D. Dalton, and C. Steger. PATMOS, volume 3254 of Lecture Notes in Computer Science, page 799-808. Springer, (2004)