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Highly Versatile DSP Blocks for Improved FPGA Arithmetic Performance., and . FCCM, page 229-236. IEEE Computer Society, (2010)Approximate quaternary addition with the fast carry chains of FPGAs., , and . DATE, page 577-580. IEEE, (2018)Exploration of approximate multipliers design space using carry propagation free compressors., , , and . ASP-DAC, page 611-616. IEEE, (2018)CAL: Exploring cost, accuracy, and latency in approximate and speculative adder design., , , and . DFT, page 1-6. IEEE Computer Society, (2017)A flexible DSP block to enhance FPGA arithmetic performance., , , , , and . FPT, page 70-77. IEEE Computer Society, (2009)Improving FPGA Performance for Carry-Save Arithmetic., , , and . IEEE Trans. VLSI Syst., 18 (4): 578-590 (2010)Fast INC-XOR codec for low-power address buses., , , and . IET Computers & Digital Techniques, 1 (5): 625-626 (2007)Measuring and Reducing the Performance Gap between Embedded and Soft Multipliers on FPGAs., and . FPL, page 225-231. IEEE Computer Society, (2011)Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs., , , , , , , and . FPGA, page 181-190. ACM, (2008)Efficient synthesis of compressor trees on FPGAs., , and . ASP-DAC, page 138-143. IEEE, (2008)