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Introduction to the Special Issue on Network-on-Chip Architectures.

M. Daneshtalab, M. Palesi, and T. Mak. Computers & Electrical Engineering, 40 (8): 257-259 (2014)

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A systematic reordering mechanism for on-chip networks using efficient congestion-aware method.M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, and H. Tenhunen. Journal of Systems Architecture - Embedded Systems Design, 59 (4-5): 213-222 (2013)Cluster-based topologies for 3D Networks-on-Chip using advanced inter-layer bus architecture.M. Ebrahimi, M. Daneshtalab, P. Liljeberg, J. Plosila, and H. Tenhunen. J. Comput. Syst. Sci., 79 (4): 475-491 (2013)Bi-LCQ: A low-weight clustering-based Q-learning approach for NoCs.F. Farahnakian, M. Ebrahimi, M. Daneshtalab, P. Liljeberg, and J. Plosila. Microprocessors and Microsystems - Embedded Hardware Design, 38 (1): 64-75 (2014)GLB - Efficient Global Load Balancing method for moderating congestion in on-chip networks.M. Daneshtalab, M. Ebrahimi, and J. Plosila. ReCoSoC, page 1-5. IEEE, (2012)Towards a Configurable Many-core Accelerator for FPGA-based embedded systems.M. Ramírez, M. Daneshtalab, P. Liljeberg, and J. Plosila. ReCoSoC, page 1-4. IEEE, (2013)Transport layer aware design of network interface in many-core systems.M. Fattah, M. Daneshtalab, P. Liljeberg, and J. Plosila. ReCoSoC, page 1-7. IEEE, (2012)Assertion based design error diagnosis for core-based SoCs.M. Kakoee, M. Neishaburi, M. Daneshtalab, and S. Safari. SoCC, page 269-272. IEEE, (2007)FPGA implementation of AES-based crypto processor.H. Anwar, M. Daneshtalab, M. Ebrahimi, J. Plosila, and H. Tenhunen. ICECS, page 369-372. IEEE, (2013)On-Chip Verification of NoCs Using Assertion Processors.M. Kakoee, M. Neishaburi, M. Daneshtalab, S. Safari, and Z. Navabi. DSD, page 535-538. IEEE Computer Society, (2007)Silicon synapse designs for VLSI neuromorphic platform.N. Phong, M. Daneshtalab, S. Dytckov, J. Plosila, and H. Tenhunen. NORCHIP, page 1-6. IEEE, (2014)

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Disambiguation of "Daneshtalab, Masoud"

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Introduction to the Special Issue on Network-on-Chip Architectures.

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PUMA

Disambiguation of "Daneshtalab, Masoud"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Introduction to the Special Issue on Network-on-Chip Architectures.

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DIN 1505
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Introduction to the Special Issue on Network-on-Chip Architectures.