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Disambiguation of "Mantovani, Paolo"

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A Switched-Inductor Integrated Voltage Regulator With Nonlinear Feedback and Network-on-Chip Load in 45 nm SOI.

, , , , , , and . J. Solid-State Circuits, 47 (8): 1935-1945 (2012)

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PD Dr. Paolo Malgaretti University of Stuttgart

Paolo Carlo Danesini University of Stuttgart

 

Other publications of authors with the same name

High-level synthesis of accelerators in embedded scalable platforms., , and . ASP-DAC, page 204-211. IEEE, (2016)Coupling latency-insensitivity with variable-latency for better than worst case design: a RISC case study., , and . ACM Great Lakes Symposium on VLSI, page 163-168. ACM, (2011)System-level memory optimization for high-level synthesis of component-based SoCs., , , and . CODES+ISSS, page 18:1-18:10. ACM, (2014)Towards a Complete Methodology for Synthesizing Bundled-Data Asynchronous Circuits on FPGAs., , , and . ISLPED, page 1-6. IEEE, (2019)Teaching Heterogeneous Computing with System-Level Design Methods., , , , , , , and . WCAE@ISCA, page 4:1-4:8. ACM, (2019)NoC-Based Support of Heterogeneous Cache-Coherence Models for Accelerators., , and . NOCS, page 1:1-1:8. IEEE, (2018)Broadening the exploration of the accelerator design space in embedded scalable platforms., , , and . HPEC, page 1-7. IEEE, (2017)Exploiting Private Local Memories to Reduce the Opportunity Cost of Accelerator Integration., , and . ICS, page 27:1-27:12. ACM, (2016)COSMOS: Coordination of High-Level Synthesis and Memory Optimization for Hardware Accelerators., , , and . ACM Trans. Embedded Comput. Syst., 16 (5s): 150:1-150:22 (2017)Accelerator Memory Reuse in the Dark Silicon Era., , , , and . IEEE Comput. Archit. Lett., 13 (1): 9-12 (2014)