Author of the publication

Enhanced architectures for soft error detection and correction in combinational and sequential circuits.

, , , and . Microelectronics Reliability, (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A parity-preserving multi-input signature analyzer and its application for concurrent checking and BIST., and . J. Electronic Testing, 8 (2): 165-177 (1996)A linear code-preserving signature analyzer COPMISR., , and . VTS, page 350-355. IEEE Computer Society, (1997)A new method for correcting time and soft errors in combinational circuits., , and . DDECS, page 283-286. IEEE Computer Society, (2013)A New Self-Checking Code-Disjoint Carry-Skip Adder., , , and . IOLTW, page 39-43. IEEE Computer Society, (2002)A New Totally Error Propagating Compactor for Arbitrary Cores with Digital Interfaces., , and . VTS, page 49-57. IEEE Computer Society, (1999)Design of self-testing and on-line fault detection combinational circuits with weakly independent outputs., and . J. Electronic Testing, 4 (3): 267-281 (1993)A New Self-Checking Sum-Bit Duplicated Carry-Select Adder., , , and . DATE, page 1360-1361. IEEE Computer Society, (2004)Synthesis of Low-Cost Parity-Based Partially Self-Checking Circuits., , , and . IOLTS, page 35-. IEEE Computer Society, (2003)On-line Fault Detection and Location for NoC Interconnects., , , , and . IOLTS, page 145-150. IEEE Computer Society, (2006)Code disjoint self-parity combinational circuits for self-testing, concurrent fault detection and parity scan design., and . VTS, page 151-157. IEEE Computer Society, (1994)