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Power-efficient hardware architecture for computing Split-Radix FFTs on highly sparsed spectrum., , , and . NEWCAS, page 1-4. IEEE, (2015)A Novel Application-specific Instruction-set Processor Design Approach for Video Processing Acceleration., , , and . VLSI Signal Processing, 47 (3): 297-315 (2007)Loop-oriented metrics for exploring an application-specific architecture design-space., , , and . ASAP, page 257-262. IEEE Computer Society, (2008)A multiprocessor architecture for multiple path stack sequential decoders., , and . IEEE Trans. Communications, 42 (234): 951-957 (1994)Design exploration with an application-specific instruction-set processor for ELA deinterlacing., , , , and . ISCAS, IEEE, (2006)Performance characterization of an SCMA decoder., , , and . NEWCAS, page 1-4. IEEE, (2016)High Acceleration for Video Processing Applications Using Specialized Instruction Set Based on Parallelism and Data Reuse., , , and . Signal Processing Systems, 56 (2-3): 155-165 (2009)A GPGPU-based software implementation of the PBDI deinterlacing algorithm., , and . ICECS, page 780-783. IEEE, (2011)A Methodology to Evaluate the Energy Efficiency of Application Specific Processors., , , and . ICECS, page 983-986. IEEE, (2007)SHIP: A Scalable High-performance IPv6 Lookup Algorithm that Exploits Prefix Characteristics., , , and . CoRR, (2017)